Low Power FFT Architectures via Folding Transformation

This paper presents a technique to develop a low power parallel-pipelined architecture for Fast Fourier Transform (FFT). A technique to design FFT architectures via folding transformation and register minimization techniques is proposed. Both complex valued FFT (CFFT) and real valued FFT (RFFT) architectures can be derived using the proposed approach. The proposed architecture for RFFT helps to reduce the hardware complexity by exploiting the redundancy present in computing the FFT samples. A comparison is made between the proposed design and the conventional architecture in terms of power consumption. The amount of power consumed can be decreased up to 50% in a 2-parallel RFFT architecture. The architectures are simulated using Verilog HDL.